On-the-fly computation method in field-programmable gate array for analog-to-digital converter linearity testing

© 2018 Published by ITB Journal Publisher. This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

A design of inverse class-J power amplifier using varactor diode for 4G communication systems

© 2018 IEEE. A Class-J Power Amplifier is designed with a varactor diode on its input matching network to improve its efficiency. To enhance the efficiency of the designed power amplifier, it is operated in inverse mode. The design, simulation, and layout generation of the circuits are implemented using the Advance Design System Tool of Keysight. Although GaN devices are known to have better performance than GaAs devices, a GaAs FET is still used as the active device for the designed power amplifier as it is more reliable compared to GaN devices. This design of Class-J power amplifier in inverse mode with varactor diode exhibits a higher power output, gain and efficiency of 30.14 dBm, 8. 14dB and 90.84%, respectively, in comparison to existing class-J power amplifier with power output of 24-27dBm, gain of 7-10 dB and efficiency of 50-5S% only. Using a One Tone Harmonic Balance Simulation for a 2GHz fundamental frequency, the resulting fundamental output power is 30. 475dBm, a transducer power gain of 6.175, a PAE of 26.943 and a gain compression of 12. 602dB. The designed power amplifier is ready to be fabricated on a Monolithic Microwave Integrated Circuit (MMIC)